Our client, a leading industrial company, is looking for a: Verification Engineer Your challengesYou will perform verification planning and be responsible for the development of the verification environment. You are in charge of functional verification and code coverage. You will define and implement test cases and implement verification of mixed-signal ASICs. Your skills Master degree in EE At least 7 years of experience in the verification of chip designs. Knowledge of following languages: Verilog, VHDL, System Verilog, UVM and SystemC is a plus. Methodology (PSL, SVA) ADA tools: Mentor Questa, Cadence NCSIM Strong knowledge in the development of chip verification environments and a proven track record of taping out chips to production. Good knowledge of scripting language (Python, CSH, Make) Experience in the development of wireless technologies is a plus. Your horizonsDo you think you have what it takes to face this challenge? Don't hesitate to contact me on adina.moraru @springprofessional.ch or apply directly on this advert. Don't think it's the right opportunity for you, but this caught your curiosity about Spring Professional? I'm waiting for your contact anyway on adina.moraru@springprofessional.ch Your contactMadame Adina Moraru, Consultant Retail, looks forward to answer your questions by phone +41 58 233 2700 or eMail. You can apply directly online, or by eMail. Please mention reference JN -022018-48525 in your application